Method for forming trench semiconductor device having schottky barrier structure

ABSTRACT

A method for forming a semiconductor device includes providing a region of semiconductor material. The method includes providing a trench structure having a trench extending into the region of semiconductor material from a first major surface, and a conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region. The method includes providing a Schottky contact region disposed adjacent to the first major surface and adjacent to the trench structure. In one example, providing the Schottky contact region comprises forming a layer of material comprising as-formed nickel-chrome; exposing the layer of material to a temperature in a range from about 400 degrees Celsius through about 550 degrees Celsius; and after the step of exposing, removing any unreacted portions of the layer of material.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation application of co-pending U.S.patent application Ser. No. 16/053,400, filed on Aug. 2, 2018, which ishereby incorporated by reference, and priority thereto is herebyclaimed.

BACKGROUND

The present invention relates, in general, to electronics and, moreparticularly, to semiconductor device structures and methods of formingsemiconductor devices.

A Schottky device is a type of semiconductor device that exhibits a lowforward voltage drop and a very fast switching action. The lower forwardvoltage drop translates into less energy wasted as heat, which providesimproved system efficiency and higher switching speed compared toconventional PN junction diodes. This makes Schottky devices moresuitable for applications requiring higher efficiency power management.

Such applications include wireless and automotive devices, boostconverters for LCD/keypad backlighting, engine control, automotivelighting, charge circuits as well as other small and large signalapplications.

With demands to further improve battery life in these applications andothers, the market is requiring even higher efficiency devices, such asSchottky devices having lower power dissipation, higher power density,and smaller die size. Some Schottky devices are formed using insulatedtrench gated structures. In such devices, a semiconductor mesa region istypically disposed between a pair of insulated trench gated structures,and the Schottky barrier is formed along the top of the semiconductormesa region. One problem with Schottky devices using insulated trenchgated structures is that upper corner regions of the semiconductor mesaregions are susceptible to stress caused by, among other things, hightemperature processing used to form the Schottky barrier structure. Suchstress issues can result in diminished device performance includingincreased leakage current.

Although Schottky devices using insulated trench gated structures haveshown improvements in performance, improvements are still needed instructures and methods that provide selectable barrier heights. Inaddition, structures and methods are needed that reduce the effects ofhigh stress particularly proximate to corner regions of semiconductormesa regions adjacent the trench gated structures.

Accordingly, it is desired to have structures and methods for providingSchottky devices with selectable barrier heights, such as Schottkydevices with insulated trench gated structures. In addition, it isdesired that the selectable barrier heights include, for example,barrier heights in a range from about 0.45 eV to about 0.85 eV.Additionally, it is desired that the structures and methods reducestress related device performance issues associated with Schottkydevices with insulated trench gates structures. Further, it is alsobeneficial for the structures and methods to be cost effective and easyto integrate into preexisting process flows. Finally, it is alsobeneficial for the structures and methods to provide design flexibilityand equal or better electrical performance compared to prior structures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a partial cross-sectional view of an example of asemiconductor device in accordance with the present description;

FIG. 2 illustrates a partial cross-sectional view of an example of asemiconductor device in accordance with the present description;

FIGS. 3 and 4 are charts illustrating comparative results of examplesemiconductor devices in accordance with the present description andprior semiconductor devices;

FIGS. 5-15 are partial cross-sectional views illustrating an examplemethod of fabricating a semiconductor device in accordance with thepresent description;

FIG. 16 illustrates a partial cross-sectional view of an example of asemiconductor device in accordance with the present description; and

FIGS. 17 and 18 are charts illustrating comparative results of examplesemiconductor devices in accordance with the present description andprior semiconductor devices.

For simplicity and clarity of the illustration, elements in the figuresare not necessarily drawn to scale, and the same reference numbers indifferent figures denote the same elements. Additionally, descriptionsand details of well-known steps and elements are omitted for simplicityof the description. As used herein, current-carrying electrode means anelement of a device that carries current through the device, such as asource or a drain of an MOS transistor, an emitter or a collector of abipolar transistor, or a cathode or anode of a diode, and a controlelectrode means an element of the device that controls current throughthe device, such as a gate of a MOS transistor or a base of a bipolartransistor. Although the devices are explained herein as certain N-typeregions and certain P-type regions, a person of ordinary skill in theart understands that the conductivity types can be reversed and are alsopossible in accordance with the present description, taking into accountany necessary polarity reversal of voltages, inversion of transistortype and/or current direction, etc. For clarity of the drawings, certainregions of device structures, such as doped regions or dielectricregions, may be illustrated as having generally straight line edges andprecise angular corners. However, those skilled in the art understandthat, due to the diffusion and activation of dopants or formation oflayers, the edges of such regions generally may not be straight linesand that the corners may not be precise angles. Furthermore, the termmajor surface when used in conjunction with a semiconductor region,wafer, or substrate means the surface of the semiconductor region,wafer, or substrate that forms an interface with another material, suchas a dielectric, an insulator, a conductor, or a polycrystallinesemiconductor. The major surface can have a topography that changes inthe x, y and z directions. As used herein, the term and/or includes anyand all combinations of one or more of the associated listed items. Inaddition, the terminology used herein is for the purpose of describingparticular examples only and is not intended to be limiting of thedisclosure. As used herein, the singular forms are intended to includethe plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms comprises,comprising, includes, and/or including, when used in this specification,specify the presence of stated features, numbers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, numbers, steps, operations,elements, components, and/or groups thereof. It will be understood that,although the terms first, second, etc. may be used herein to describevarious members, elements, regions, layers and/or sections, thesemembers, elements, regions, layers and/or sections should not be limitedby these terms. These terms are only used to distinguish one member,element, region, layer and/or section from another. Thus, for example, afirst member, a first element, a first region, a first layer and/or afirst section discussed below could be termed a second member, a secondelement, a second region, a second layer and/or a second section withoutdeparting from the teachings of the present disclosure. It will beappreciated by those skilled in the art that words, during, while, andwhen as used herein related to circuit operation are not exact termsthat mean an action takes place instantly upon an initiating action butthat there may be some small but reasonable delay, such as propagationdelay, between the reaction that is initiated by the initial action.Additionally, the term while means a certain action occurs at leastwithin some portion of a duration of the initiating action. The use ofword about, about or substantially means a value of an element isexpected to be close to a state value or position. However, as is wellknown in the art there are always minor variances preventing values orpositions from being exactly stated. Unless specified otherwise, as usedherein the word over or on includes orientations, placements, orrelations where the specified elements can be in direct or indirectphysical contact. Unless specified otherwise, as used herein the wordoverlapping includes orientations, placements, or relations where thespecified elements can at least partly or wholly coincide or align inthe same or different planes. It is further understood that the examplesillustrated and described hereinafter suitably may have examples and/ormay be practiced in the absence of any element that is not specificallydisclosed herein.

DETAILED DESCRIPTION OF THE DRAWINGS

In general, the present embodiments relate to a semiconductor device andmethod of forming the semiconductor device having a Schottky contactregion formed from a conductive structure, such as a combination ofconductive materials capable of forming silicides including titanium andnickel-platinum. In some examples, a layer of titanium is provided firstfollowed by a layer of nickel-platinum. The combination of conductivematerials is then exposed to a predetermined elevated temperature toform one or more silicide regions within the semiconductor device. Inanother example, the conductive structure includes a combination ofmaterials that comprises a nickel-chrome alloy layer, which issubsequently exposed to a predetermined elevated temperature to form oneor more silicide regions within the semiconductor device. In someexamples, the nickel-chrome alloy is an as-deposited mixture orcombination of nickel and chrome.

The Schottky contact regions in accordance with the present descriptionprovide predetermined Schottky barrier heights within a desired 0.45 eVto 0.85 eV range, provide a semiconductor device with improved powerdissipation in certain applications, and provide a semiconductor devicewith reduced stress-related defects, which, among other things, reducesleakage current. In addition, the Schottky contact regions in accordancewith the present description reduce the amount of silicide migration inthe area of the trench gate oxide, which further improves deviceperformance. The reduced silicide migration is one important factor inobtaining proper device function in Schottky devices using insulatedtrench gated structures. The structure and method can be easilyimplemented into existing process flows, which saves on manufacturingcosts and cycle time.

In some examples, the combination of materials consists essentially of alayer of titanium and a layer of nickel-platinum (with various levels ofPt, including, for example, 5%, 15%, 60%, 80%)). In other examples, thecombination of materials consists of a layer of titanium and a layer ofnickel-platinum (with various levels of Pt, including, for example, 5%,15%, 60%, 80%). In further examples, it is preferred that the as-formed(i.e., before silicide is formed) thickness ratio of titanium tonickel-platinum be greater than or equal to about 1.33:1. In otherpreferred examples, it is the preferred that the as-formed thicknessratio be greater than or equal to about 2:1. In some preferred examples,the as-formed thickness ratio be greater than or equal to 3:1. Infurther preferred examples, the as-formed thickness ratio be about 6:1.In other examples, the combination of materials comprises nickel-chrome(for example, a 40% nickel/60% chrome alloy). In further examples, thecombination of material consists essentially of nickel-chrome (forexample, a 40% nickel/60% chrome alloy). In still further examples, thecombination of materials consists of nickel-chrome (for example, a 40%nickel/60% chrome alloy).

More particularly, a method of forming a semiconductor device comprisesproviding a region of semiconductor material comprising a first majorsurface and a second major surface opposite to the first major surface.The method includes providing a trench structure comprising a trenchextending into the region of semiconductor material from the first majorsurface; and a conductive material disposed within the trench andseparated from the region of semiconductor material by a dielectricregion. The method includes providing a Schottky contact region disposedadjacent to the first major surface and adjacent to the trenchstructure, wherein providing the Schottky contact region includesforming a first layer of material disposed adjacent to the first majorsurface, the first layer of material comprising titanium and having afirst thickness; forming a second layer of material disposed adjacent tothe first layer of material, the second layer of material comprisingnickel-platinum and having a second thickness; exposing the first layerof material and the second layer of material to a temperature in a rangefrom about 650 degrees Celsius through about 700 degrees Celsius; andafter the step of exposing, removing any unreacted portions of the firstlayer of material and the second layer of material.

In another example, a method of forming a semiconductor device includesproviding a region of semiconductor material comprising a first majorsurface and a second major surface opposite to the first major surface.The method includes providing a trench structure comprising a trenchextending into the region of semiconductor material from the first majorsurface; and a conductive material disposed within the trench andseparated from the region of semiconductor material by a dielectricregion, wherein the dielectric region is disposed along opposingsidewall surfaces of the trench and disposed along a lower surface ofthe trench; and the dielectric region comprises a first uppermostsurface. The method includes providing a Schottky contact regiondisposed adjacent to the first major surface and adjacent to the trenchstructure, wherein providing the Schottky contact region comprisesforming a first layer of material disposed adjacent to the first majorsurface, the first layer of material consisting essentially of titaniumand having a first thickness; forming a second layer of materialdisposed adjacent to the first layer of material, the second layer ofmaterial consisting essentially of nickel-platinum and having a secondthickness; exposing the first layer of material and the second layer ofmaterial to a temperature in a range from about 650 degrees Celsiusthrough about 700 degrees Celsius; and after the step of exposing,removing any unreacted portions of the first layer of material and thesecond layer of material.

In a further example, a method of forming a semiconductor devicecomprises providing a region of semiconductor material comprising afirst major surface and a second major surface opposite to the firstmajor surface. The method includes providing a trench structurecomprising a trench extending into the region of semiconductor materialfrom the first major surface; and a conductive material disposed withinthe trench and separated from the region of semiconductor material by adielectric region, wherein the dielectric region is disposed alongopposing sidewall surfaces of the trench and disposed along a lowersurface of the trench; and the dielectric region comprises a firstuppermost surface. The method includes providing a Schottky contactregion disposed adjacent to the first major surface and adjacent to thetrench structure, wherein providing the Schottky contact regioncomprises forming a conductive structure, the conductive structure beingone of: 1) a layer of material consisting essentially of nickel-chromedisposed adjacent to the first major surface; or 2) a first layer ofmaterial consisting essentially of titanium disposed adjacent to thefirst major surface and a second layer of material disposed adjacent tothe first layer of material and consisting essentially ofnickel-platinum; exposing the conductive structure to an elevatedtemperature to form a silicide structure; and after the step ofexposing, removing any unreacted portions of the conductive structure.

FIG. 1 illustrates an enlarged partial cross-sectional view of anelectronic device 10, a semiconductor device 10, Schottky diode device10, or trench Schottky rectifier 10 in accordance with one example. Inthe present example, device 10 includes a region of semiconductormaterial 11, which includes a major surface 18 and major surface 19,which is opposite to major surface 18. Region of semiconductor material11 can include a bulk substrate 12, such as an N-type silicon substratehaving a resistivity ranging from about 0.001 ohm-cm to about 0.005ohm-cm. By way of example, substrate 12 can be doped with phosphorous,arsenic, or antimony.

Device 10 further includes a semiconductor layer 14, doped region 14, ordoped layer 14, which can be formed in, on, or overlying substrate 12.In one example, semiconductor layer 14 can be an N-type conductivityregion or layer, and can be formed using epitaxial growth techniques,ion implantation and diffusion techniques, or other techniques known tothose of ordinary skill in the art. In one example, semiconductor layer14 includes major surface 18 of region of semiconductor material 11. Insome examples, semiconductor layer 14 has a dopant concentration lessthan the dopant concentration of substrate 12. The dopant concentrationand/or dopant profile of semiconductor layer 14 can be selected toprovide a desired breakdown voltage and a desired forward voltage drop.It is understood that region of semiconductor material 11, semiconductorsubstrate 12, and/or semiconductor layer 14 can include other types ofmaterials including, but not limited to, heterojunction semiconductormaterials, and semiconductor substrate 12 and semiconductor layer 14 caneach include different materials. Such materials can include SiGe,SiGeC, SiC, GaN, AlGaN, and other similar materials as known to those ofordinary skill in the art.

Device 10 includes a first trench 21 or termination trench 21 and secondtrenches 23 or active trenches 23. By way of example, termination trenchstructure 21 can be disposed in or adjacent to an edge portion of regionof semiconductor material 11, and active trenches 23 can be disposedinward from termination trench 21 such that termination trench structure21 is interposed between the edge portion of region of semiconductormaterial 11 and active trenches 23. In some examples, termination trench21 is a continuous trench that completely surrounds active trenches 23.In one example, termination trench 21 extends from major surface 18 intosemiconductor layer 14 towards semiconductor substrate 12. In someexamples, termination trench 21 can extend into semiconductor substrate12. In other examples, termination trench 21 can terminate withinsemiconductor layer 14 thereby leaving a portion of semiconductor layer14 disposed between a lower extent of termination trench 21 andsemiconductor substrate 12. In one example, termination trench 21includes a dielectric layer 212, a dielectric region 212, or adielectric structure 212 disposed adjoining sidewall and lower surfacesof termination trench 21 as generally illustrated in FIG. 1.

Dielectric layer 212 defines a lower surface 210 of termination trench21 at a distance inward from major surface 18. It is understood thatlower surface 210 may not be flat, but may have other shapes including,but not limited to curved, rounded, partially-curved, orpartially-rounded shapes. In one example, dielectric layer 212 can be athermal oxide having a thickness in a range from about 0.05 microns toabout 0.5 microns. In other examples, dielectric layer 212 can be othertypes of oxides, nitrides, combinations thereof, or other materialsknown to those skilled in the art.

In one example, termination trench 21 further includes one or moreconductive spacers 217 along sidewall surfaces adjoining dielectriclayer 212. In one example, conductive spacers 217 can be a conductivepolycrystalline material, such as a doped polysilicon (e.g., N-type orP-Type). In one example, a dielectric layer 219, a dielectric region219, or a dielectric structure 219 is disposed within termination trench21. In one example, dielectric layer 219 can be further disposed on oradjacent to a portion of major surface 18 laterally spaced away fromactive trenches 23 as generally illustrated in FIG. 1. In one example,dielectric layer 219 can be a deposited dielectric material, such as adeposited oxide, a deposited nitride, combinations thereof, or otherdielectric materials as known to those skilled in the art. In onepreferred example, dielectric layer 219 can be an oxide deposited usinga tetra-ethyl-ortho-silicate (“TEOS”) source using plasma-enhancedchemical vapor deposition (“PECVD”) or low pressure chemical vapordeposition (“LPCVD”), and can have a thickness in a range from about 0.2microns to about 1.0 micron. In some examples, termination trench 21 canhave a width in a range from about 4 microns to about 20 microns. In oneexample, termination trench 21 can have a width of about 10 microns.

In the present example, device 10 includes active trenches 23 extendingfrom major surface 18 into semiconductor layer 14 towards semiconductorsubstrate 12. In some examples, active trenches 23 are configured as aplurality of separate trenches. In other examples, active trench 23 canbe configured as a continuous trench. In one example, active trenches 23include a gate dielectric region 222, a gate dielectric layer 222, adielectric layer 222, a dielectric layer 222, a dielectric region 222,or a dielectric structure 222 disposed adjoining sidewall and lowersurfaces of active trenches 23. Dielectric layer 222 defines a lowersurface 230 of active trenches 23. It is understood that lower surfaces230 may not be flat, but can have other shapes including, but notlimited to curved, rounded, partially-curved, or partially-roundedshapes. In one example, dielectric layers 222 comprise a thermal oxidehaving a thickness in a range from about 0.05 microns to about 0.6microns. In some examples, dielectric layer 212 and dielectric layers222 can be the same material. In some examples, dielectric layer 212 anddielectric layer 222 can be formed during the same process step.

Active trenches 23 further include a conductive layer 237, a conductiveregion 237, a gate electrode 237, or a conductive material 237 providedalong surfaces adjoining dielectric layer 222. In one example,conductive material 237 can be a conductive polycrystalline material,such as a doped polysilicon. In some examples, active trenches 23 canhave a width in a range from about 0.1 microns to about 0.6 microns. Inone example, active trenches 23 can have a width of about 0.2 microns toabout 1.0 micron. By way of example, the width of active trenches 23 canbe modified depending on the breakdown voltage rating of device 10. Insome examples, device 10 can have an active trench 23 width totermination trench 21 width ratio in a range from about 0.005 to about0.125. In other examples, device 10 can have an active trench 23 widthto termination trench 21 width ratio less than about 0.03.

In some examples, dielectric layers 222 comprise uppermost surfaces 222Aand 222B that are intentionally shaped or formed having a profile in across-sectional view where a major portion or a substantial portion(e.g., at least 50% or more) of uppermost surfaces 222A and 222B resideabove a generally horizontal plane defined by major surface 18 of regionof semiconductor material 11 (or semiconductor layer 14) prior to theformation of Schottky contact regions 26, which are described next.

Device 10 further includes Schottky contact regions 26, Schottky barrierstructures 26, contact regions 26, conductive layers 26, conductiveregion or regions 26, or conductive material 26 disposed adjoiningportions of major surface 18. In some examples, Schottky contact regions26 also can be disposed adjoining upper surface portions of conductivematerial 237 and upper surface portions of at least one of conductivespacers 217. Conductive material 26 comprises materials capable offorming a silicide with region of semiconductor material 11, andconfigured to provide a Schottky barrier with region of semiconductormaterial 11 or semiconductor layer 14.

In accordance with the present description, Schottky contact regions 26comprise a combination of conductive materials configured to provide apredetermined Schottky barrier height in a desired range. Moreparticularly, the combination of metal materials is selected andprocessed to provide a predetermined Schottky barrier height in a rangefrom about 0.45 eV to about 0.85 eV. In one preferred example, Schottkycontact regions 26 comprise a combination of titanium (Ti) and an alloyof nickel-platinum (NiPt), with various platinum atomic weightpercentages, for example, from about 1% to about 80%, with 5% beingselected in some examples. In accordance with one preferred example asillustrated in FIG. 2, which is a partial cross-sectional view of device10 at an earlier step in fabrication, Schottky contact regions 26initially comprise a layer 26A of titanium deposited overlying majorsurface 18 followed by a layer 26B of nickel-platinum depositedoverlying layer 26A of titanium. Layers 26A and 26B may be referredtogether as a conductive structure 1126.

In some examples, layer 26A of titanium is formed using sputteringtechniques, and has an as-formed thickness in a range from about 200Angstroms through about 1000 Angstroms. In other examples, layer 26A oftitanium has an as-formed thickness in a range from about 300 Angstromsthrough about 800 Angstroms. In further examples, layer 26A of titaniumhas an as-formed thickness in a range from about 400 Angstroms throughabout 600 Angstroms. In further examples, it is preferred that theas-formed (i.e., before silicidation) thickness ratio of titanium tonickel-platinum be greater than or equal to about 1.33 to 1 (1.33:1). Inother preferred examples, he as-formed thickness ratio be greater thanor equal to about 2:1. In some preferred examples, the as-formedthickness ratio is greater than or equal to 3:1. In further preferredexamples, the as-formed thickness ratio is about 6:1.

In some examples, layer 26B of nickel-platinum is formed usingsputtering techniques, and has a thickness in a range from about 50Angstroms through 400 Angstroms. In other examples, layer 26B ofnickel-platinum has a thickness in a range from about 100 Angstromsthrough about 350 Angstroms. In accordance with the present description,after layer 26B is formed, layers 26A and 26B are exposed to an elevatedtemperature to form a silicide layer with region of semiconductormaterial 11. More particularly, conductive material 26 preferably isexposed to or annealed at a temperature in a range from 650 degreesCelsius through about 700 degrees Celsius in the presence of a gas thatdoes not readily form reaction products with other materials, such asthose used in device 10. By way of example, the annealing step is donein nitrogen. In one example, a rapid thermal annealing process can beused with conductive material 26 exposed to the predeterminedtemperature between about 650 degrees Celsius and about 700 degreesCelsius for a time period of about 30 seconds to about 45 seconds. Itwas found through experimentation that temperatures in excess of about700 degrees Celsius can result in stress at the upper corners 141 of themesa regions 140 of device 10 adjacent to dielectric layers 222 ofactive trenches 23, which can result in diminished electricalperformance.

After the anneal step is completed, the annealed material is exposed toa stripping or removal process to remove any unreacted material toSchottky contact regions 26 for device 10. In some examples, theannealed material is exposed to a wet chemical bath comprising sulfuricacid and hydrogen peroxide (SPM). In some examples, the wet chemicalbath is heated to temperatures in excess of 100 degrees Celsius. Inother examples, a wet chemical bath heated to a temperature of about 150degrees Celsius is used to remove unreacted material to provide Schottkycontact regions 26. In further examples, a mixture of nitric acid andhydrochloric acid (for example, aqua regia) or ammonium peroxide can beused to remove unreacted material.

In some examples, device 10 may also include one or more doped regions31, which can be either N-type or P-type provided adjacent to majorsurface 18 and adjacent to Schottky contact regions 26. In one example,doped regions 31 can be deeper doped regions having a dopantconcentration configured to provide clamping action in reverse biasconditions to improve the dynamic robustness of device 10. In otherexamples (as illustrated in FIG. 2), doped region 31 can be a shallowerdoped region that extends laterally across semiconductor layer 14adjacent major surface 18, and can have a dopant concentrationconfigured to further adjust barrier height(s) for device 10. Dopedregions 31 can be provided using ion implantation and annealingtechniques, epitaxial growth techniques, or other doping techniques asknown to those skilled in the art. In one example, doped regions 31extend into region of semiconductor material 11 so as to be deeper thanthe bottoms of active trenches 23 when doped regions 31 are used fordynamic clamping or conduction tuning.

In other examples, doped regions 31 can be provided in only some mesaregions and not in others to provide different Schottky barrier heightsbetween mesa regions. When doped region 31 are used for further barrierheight adjustment, doped regions 31 typically have depth less than about1.0 micron.

In some examples, device 10 may include a deeper doped region (notillustrated) provided below doped regions 31 to provide for conductiontuning of the device. This may also be done by providing, for example, agraded dopant profile within semiconductor layer 14 by using gradedepitaxial growth techniques or by using multiple ion implants.

In some examples, device 10 may include a doped region 30 or an edgeseal region 30 disposed between termination trench 21 and the edge orperiphery of region of semiconductor material 11. In some examples,doped region 30 comprises the same conductivity type as semiconductorlayer 14, which in the present example is N-type, and can be formedusing ion implantation and annealing processes. In some examples, dopedregion 30 is heavily doped to provide low contact resistance toconductive layer 44. Doped region 30 can be P-type when semiconductorlayer 14 is P-type. Doped region 30 can be configured to reduce leakagecurrent issues caused by, for example, edge defects. It is understoodthat doped region 30 may not be included in some examples. In someexamples, a Schottky contact region 26 may also be disposed adjoiningdoped region 30 adjacent to major surface 18 of region of semiconductor11 as generally illustrated in FIG. 1.

A conductive layer 44 can be formed overlying major surface 18 and aconductive layer 46 can be formed overlying major surface 19. Conductivelayers 44 and 46 can be configured to provide electrical connectionbetween device 10 and a next level of assembly, such as a semiconductorpackage structure or substrate. In accordance with the present example,conductive layer 44 is electrically connected to Schottky contactregions 26. In one example, conductive layer 44 can betitanium/titanium-nitride/aluminum-copper or other related or equivalentmaterials known by one of ordinary skill in the art and is configured asfirst current carrying electrode or terminal 440 or an anode electrode440 for device 10. In one example, conductive layer 46 can be asolderable metal structure such as titanium-nickel-silver,chromium-nickel-gold, or other related or equivalent materials known bythose skilled in the art. In the example illustrated, conductive layer46 provides a second current carrying electrode or terminal 460 or acathode electrode 460 for device 10.

In accordance with the present example, Schottky contact regions 26comprising titanium and nickel-platinum as described herein were foundthrough experimentation to provide Schottky barrier heights in a desiredrange from about 0.5 eV to about 0.8 eV with reduced stress in regionsof device 10 proximate to the corner regions 141 of mesa regions 140between active trenches 23.

FIGS. 3 and 4 are box and whisker charts illustrating experimentalresults comparing two variations of device 10 in accordance with thepresent description with prior device using a titanium only Schottkybarrier structure and a prior device using a nickel-platinum onlySchottky barrier structure. FIG. 3 compares reverse leakage data andFIG. 4 compares Schottky barrier height data. In the analysis,semiconductor layer 14 comprised an epitaxially formed layer having athickness of about 2.8 microns and a resistivity (N-type) of about 0.14Ohm-cm. In both FIGS. 3 and 4, column A is data from two wafers of aprior device with a Schottky barrier structure formed from a layer oftitanium having an as-formed thickness of 700 Angstrom; column B is datafrom two wafers of a device 10 in accordance with the presentdescription having a Schottky barrier structure 26 formed from a layerof titanium having an as-formed thickness of about 400 Angstroms and alayer of nickel-platinum (5% Pt) having an as-formed thickness of about200 Angstroms; column C is data from two wafers of a device 10 inaccordance with the present description having a Schottky barrierstructure 26 formed from a layer of titanium having an as-formedthickness of about 600 Angstroms and a layer of nickel-platinum havingan as-formed thickness of about 100 Angstroms; and column D is data fromtwo wafers of a prior device with a Schottky barrier structure formedfrom a layer of nickel-platinum (5% Pt) having an as-formed thickness of700 Angstroms.

As this data illustrates, device 10 in accordance with the presentdescription provides predetermined Schottky barrier heights within therange of 0.45 eV to 0.85 eV. In particular, the examples illustratedprovide barrier heights in a range from about 0.62 eV to about 0.68 eVwith acceptable leakage current results.

In addition, the authors of the present description found at least oneunexpected result through their experimentation. More particularly, theauthors found that a thicker titanium layer for layer 26A and a thinnernickel-platinum layer 26B (e.g., the column C structure) actuallyproduced a Schottky barrier height that is closer to the column D devicehaving a nickel-platinum only Schottky barrier structure. As the datashows, the column B device, which has less titanium and morenickel-platinum than the column C devices, is closer to the titaniumonly Schottky barrier structure of column A. The authors assert that hadone of ordinary skill in the art considered the author's invention atthe time the authors conceived it, one of ordinary skill in the artwould have predicted that a thicker titanium film would have been closerto the characteristics of a titanium only Schottky barrier structure.Through their work, the authors discovered that this is not the case,which was unexpected.

It is believed that a thicker titanium layer forms a larger titaniumgrain boundary, which allows more nickel-platinum silicide to form onthe surface, resulting in a higher barrier height. This behavior isopposite to what is expected from a typical mixture of titanium andnickel-platinum because titanium has a lower barrier height thannickel-platinum. It is also observed that thinner titanium filmthickness results in less nickel-platinum silicidation, which leads tolower barrier height, which is more in-line with expected results.

In addition, Table 1 provides further comparison results for a device 10in accordance with the present description having atitanium/nickel-platinum (5% Pt) Schottky barrier structure against acomparable planar device having a nickel-platinum Schottky barrierstructure, an insulated trench gated device with a nickel-platinum (5%Pt) Schottky barrier structure, and an insulated trench gated devicewith a titanium Schottky barrier structure. These results show thatdevice 10 has, among other things, improved VF performance and improvedpower dissipation performance compared to the planar Schottky device andthe nickel-platinum (5%) only device; and has improved reverse leakagecurrent (IR) performance compared to the titanium only device.

TABLE 1 Comparison Electrical Data for Device 10 600Ti/ NiPt (5%)200NiPt Insulated Insulated Ti Insulated trench gated trench gatedtrench gated Planar Schottky Schottky Schottky Schottky device devicedevice Die Size 330 um × 330 um × 330 um × 330 um × 260 um 260 um 260 um260 um BVR @ 1 mA 50 V 48 V 48 V 48 V IR @ 10 V 0.78 uA 0.17 uA 1.2 uA20.1 uA IR @ 30 V 2.3 uA 1.1 uA 2.4 uA 50 uA VF @ 500 mV 780 mV 580 mV530 mV 445 mV Calculated 27.7 mW 20.5 mW 18.9 mW 17.2 mW PowerDissipation (PD) PD 100% 74% 68% 62% Comparison

Turning now to FIGS. 5-15, an example method for forming a semiconductordevice, such as device 10, will now be described. In FIG. 5, which is apartial cross-section view of device 10 at an early step in fabrication,region of semiconductor material 11 is provided having substrate 12 withmajor surface 19′ and semiconductor layer 14 with major surface 18. Inone example, substrate 12 can be an N-type silicon substrate having aresistivity ranging from about 0.001 ohm-cm to about 0.005 ohm-cm andcan be doped with arsenic. In one example, semiconductor layer 14 isprovided using epitaxial growth techniques and can be provided having athickness 51 in a range from about 1.0 microns to about 15 microns. Insome examples, semiconductor layer 14 has a thickness in a range fromabout 1 micron to about 15 microns, and a dopant concentration in arange from about 5.0×10¹³ atoms/cm³ to about 5.0×10¹⁷ atoms/cm³. In someexamples, semiconductor layer 14 is N-type and doped with phosphorous.

More particularly, in an example for a 20 volt device, semiconductorlayer 14 has a thickness 51 from about 1.5 microns to about 2.5 micronsand a dopant concentration in a range from about 1.0×10′⁶ atoms/cm³ andabout 1.0×10′⁷ atoms/cm³. In an example for a 30 volt device,semiconductor layer 14 has a thickness 51 from about 2.25 microns toabout 3.25 microns and a dopant concentration in a range from about1.5×10¹⁶ atoms/cm³ and about 8.0×10¹⁶ atoms/cm³. In an example for a 40volt device, semiconductor layer 14 has a thickness 51 from about 2.7microns to about 4.5 microns and a dopant concentration in a range fromabout 1.0×10¹⁶ atoms/cm³ and about 6.0×10¹⁶ atoms/cm³.

In some examples, semiconductor layer 14 has a substantially uniformdopant profile along or over its thickness 51. In other examples,semiconductor layer 14 has a non-uniform dopant profile along or overthickness 51. For example, semiconductor layer 14 can have a gradeddopant profile where the dopant concentration can decrease from majorsurface 18 over thickness 51 towards substrate 12. In another example,the dopant concentration can increase over thickness 51 from majorsurface 18 towards substrate 12. In yet another example, the dopantconcentration can first increase and then decrease over thickness 51from major surface 18 towards substrate 12.

FIG. 6 illustrates device 10 after additional processing. In oneexample, the structure is subjected to a cleaning process and then alayer 61 can be provided adjacent to or overlying major surface 18. Insome examples, layer 61 can be a dielectric material, such as an oxideor another material configured for providing a hard mask. In oneexample, layer 61 is a thermal oxide having a thickness in a range fromabout 0.03 microns to about 0.5 microns. A masking layer 62 is thenprovided disposed overlying layer 61 as illustrated in FIG. 7. In oneexample, masking layer 62 can be a photoresist layer patterned toprovide an opening 610 configured in a desired pattern to provide fordoped region 30 or edge seal region 30. In one example, doped region 30is then provided using ion implantation techniques or other dopingtechniques. In some examples, doped region 30 is provided using anarsenic ion implant with an implant dose of about 1.0×10¹⁵ atoms/cm² toabout 7.0×10¹⁵ atoms/cm² and an implant energy of about 100 keV. In someexamples, masking layer 62 is then removed. The implanted dopant can beannealed at this step in the process, and/or it can be annealed at asubsequent process step. In some examples, doped region 30 is not used.

FIG. 8 illustrates device 10 after further processing. In one example,the structure is cleaned and a layer 612 is provided overlying majorsurface 18. In some examples, layer 612 can be a dielectric layercomprising a thermal oxide having a thickness in a range from about 0.15microns to about 0.5 microns. In some examples, layer 612 has athickness that allows for dopants to be effectively or desirablyimplanted through the layer 612 into semiconductor layer 14. Next, amasking layer 622 is provided disposed overlying layer 612. In oneexample, masking layer 622 comprises a photoresist layer patterned toprovide openings 611A, 611B, and 611C for doped regions 31, which canhave the same or different dimensions. In example, doped regions 31 arethen provided using ion implantation techniques. In some examples, dopedregions 31 are provided using a boron ion implant with an implant doesof about 6.0×10¹² atoms/cm² to about 1.0×10¹³ atoms/cm² and an implantenergy of 300 keV. In some examples, masking layer 622 is then removed.The implanted dopant can be annealed at this step in the process, and/orit can be annealed at a subsequent process step. In some examples, dopedregions 31 are not used.

FIG. 9 illustrates device 10 after still further processing. In oneexample, a masking layer (not shown), such as a patterned photoresistlayer, is provided over layer 612. The masking layer is then used toform openings 613A and 613B in layer 612 exposing, for example, portionsof major surface 18 of region of semiconductor material 11. In someexamples, opening 613A can have a width in a range from about 4 micronsto about 20 microns, and openings 613B can have a width in a range fromabout 0.1 microns to about 2 microns.

In some examples, a single removal step is used to form both terminationtrench 21 and active trenches 23, which can have different depths. Insome examples, termination trench 21 is deeper than active trenches 23.In other examples, active trenches 23 are deeper than termination trench21. In one example, termination trench 21 and active trenches 23 can beetched using plasma etching techniques with a fluorocarbon chemistry ora fluorinated chemistry (for example, SF₆/O₂) or other chemistries orremoval techniques as known to those skilled in the art. Active trenches23 can have a depth in a range from about 0.4 microns to about 4.0microns. Termination trench 21 can have a depth in a range from about0.8 microns to about 10.0 microns.

FIG. 10 illustrates device 10 after additional processing. In oneexample, a layer 81 is formed along surfaces of termination trench 21,surfaces of active trenches 23, and major surface 18. In one example,layer 81 is a dielectric material, such as an oxide, a nitride, tantalumpentoxide, titanium dioxide, barium strontium titanate, high kdielectric materials, combinations thereof, or other related orequivalent materials known those skilled in the art. In one example,layer 81 can be a dry oxide having a thickness in a range from about0.05 microns to about 1.0 micron. In some examples, layer 81 has athickness of about 0.4 microns. More particularly, the thickness oflayer 81 is selected to leave a gap between adjacent surfaces of layer81 within active trenches 23 as generally illustrated in FIG. 10. Inother examples, the sidewall surfaces of termination trench 21 can besloped to provide further field shaping effects. In other examples,portions of layer 612 can remain adjacent major surface 18 betweentermination trench 21 and the outermost edge of region of semiconductormaterial 11.

Next, a conductive layer 82 is provided adjacent to or overlying layer81. In some examples, conductive layer 82 comprises doped polysiliconprovided using LPCVD or PECVD processing techniques. In one example,conductive layer 82 is provided using a silane source gas doped with anN-type dopant, such as phosphorous. In some examples, conductive layer82 has a thickness in a range from about 0.6 microns to about 2.0microns, and has a dopant concentration of 1.0×10²⁰ atoms/cm³ or more.One artifact of the present method is that notches 820 are formed in thetop surface of conductive layer 82 disposed above active trenches 23. Itwas found through experimentation that notches 820 are a factor indefining the shape of uppermost surfaces 222A and 222B of dielectricregions 222. In prior methods, a blanket or unmasked etch-back step wasused to planarize conductive layer 82 all the way back to layer 81. Thatis, the blanket etch-back step was done until conductive layer 82 wascleared or removed from layer 81 above the horizontal portions of majorsurface 18. The author's experimentation found that among other things,unless accounted for, notches 820 can result in the uppermost surfacesof dielectric regions 222 to have a downward sloping shape from edges141 of mesas 140 towards conductive material 237. This downward slopingshape resulted in, among other things, a semiconductor device havingincreased leakage and reduced breakdown voltage performance.

FIG. 11 illustrates device 10 after further processing. In accordancewith the present example, up to about 75% to 85% of conductive layer 82is removed using the blanket etch process to provide conductive layer82′. In one example, a wet etch can be used. In other examples, a dryetch can be used. In some examples, about 0.14 microns to about 0.16microns of conductive layer 82 remains after the blanket etch process.In one preferred example, about 0.15 microns of conductive layer 82remains after the blanket etch process. In some examples, this thicknesswas found to provide better electrical performance for device 10including lower leakage and improved breakdown voltage. Because of thelarger width of termination trench 21, in some examples the portion ofconductive layer 82 at the bottom of termination trench 21 can clear oretch away thereby leaving conductive spacers 217 proximate to sidewallsurfaces of termination trench 21 as generally illustrated in FIG. 11.In a next process step, the remaining 15% to 25% of conductive layer 82is removed using chemical mechanical planarization (CMP) techniquesusing layer 81, in some examples, as a stop layer to provide theintermediate structure illustrated in FIG. 12.

In some examples, a remaining portion of conductive layer 82 ispre-cleaned prior to the CMP process to remove any unwanted, residual,native, or remaining film(s) on conductive layer 82 that would impedethe CMP process. One result from this added step is that portions ofconductive layer 82 (which are left within active trenches 23 to provideconductive material 237) can have a flared-out portion 2370 at the upperportion of conductive material 237 proximate to active trenches 23. Inthe previous method, conductive material 82 was recessed below the uppersurface of layer 81 because of etch control or required over-etching. Inother examples, a first portion of conductive layer 82 is removed usingCMP, preferably below notches 820, and then a blanket etch is used toremove second or remaining portion of conductive layer 82 back to layer81.

FIG. 13 illustrates device 10 after still further processing. In someexamples, a layer of material is provided adjacent major surface 18. Inone example, the layer of material can be a TEOS oxide deposited using aPECVD process or an LPCVD process, and can have thickness in a rangefrom about 0.35 microns to about 0.7 microns. Next, a contact maskingstep and removal step can be used to leave a portion of the layer ofmaterial within termination trench 21 to provide dielectric layer 219.The masking and removal steps can further remove portions of layer 81from the active region of device 10 to expose portions of major surface18 to provide contact regions 118 and to provide an opening 2191 todoped region 30. This step provides dielectric layer 212 withintermination trench 21 and dielectric layers 222 within active trenches23. The masking and removal steps can also remove portions of conductivematerial 237 within active trenches 23 to provide the upper surfaces ofconductive material 237 at a desired location within active trenches 23.

In some examples, flared-out portions 2370 beneficially result in all orsubstantially all of uppermost surfaces 222A and 222B to be above ahorizontal plane 182 with respect to major surface 18 after the maskingand removal step. In other examples, the mask used to provide contactregions 118 is modified to protect portions of layer 81 proximate toactive trenches 23 to provide other shapes for uppermost regions 222Aand 222B. This can be combined with removal steps, such as selectiveetching, directional milling or etching, or anisotropic etching toprovide the desired shapes of uppermost regions 222A and 222B. Theresulting shapes of uppermost surfaces 222A and 222B of dielectricregions 222 provide device 10 with improved performance and reliability.

FIG. 14 illustrates device 10 after additional processing in accordancewith the present description where layer 26A of conductive material isprovided overlying major surface 18 and layer 26B of conductive materialis provided overlying layer 26A. More particularly, layer 26A makesdirect physical contact to region of semiconductor material 11 adjacentto major surface 18.

In some examples, as-formed layer 26A comprises titanium formed usingsputtering techniques. In other examples, as-formed layer 26A consistsessentially of titanium formed using sputtering techniques. In furtherexamples, as-formed layer 26A consists of titanium formed usingsputtering techniques. In some examples, as-formed layer 26B comprisesnickel-platinum (e.g., 5% Pt; 15% Pt; 60% Pt) formed using sputteringtechniques. In other examples, as-formed layer 26B consists essentiallyof nickel-platinum (e.g., 5% Pt; 15% Pt; 60% Pt) formed using sputteringtechniques. In further examples, as-formed layer 26B consists ofnickel-platinum (e.g., 5% Pt; 15% Pt; 60% Pt) formed using sputteringtechniques. It is understood that other deposition or formationtechniques as known to those skilled in that art can be used to form orprovide layers 26A and 26B.

In some examples, layer 26A has an as-formed thickness in a range fromabout 200 Angstroms through about 1000 Angstroms. In other examples,layer 26A has an as-formed thickness in a range from about 300 Angstromsthrough about 800 Angstroms. In further examples, layer 26A has anas-formed thickness of about 400 Angstroms through about 600 Angstroms.

In some examples, layer 26B has an as-formed thickness in a range fromabout 50 Angstroms through 400 Angstroms. In other examples, layer 26Bhas an as-formed thickness in a range from about 100 Angstroms throughabout 350 Angstroms. In one preferred example, layer 26A has anas-formed thickness of about 600 Angstroms and layer 26B has anas-formed thickness of about 100 Angstroms. In another preferredexample, layer 26A has an as-formed thickness of about 400 Angstroms andlayer 26B has an as-formed thickness of about 200 Angstroms. In furtherexamples, it is preferred that the as-formed (i.e., before silicide isformed) thickness ratio of titanium to nickel-platinum be greater thanor equal to about 1.33:1. In other preferred examples, the as-formedthickness ratio be greater than or equal to about 2:1. In some preferredexamples, the as-formed thickness ratio be greater than or equal toabout 3:1. In further preferred examples, it is preferred that theas-formed thickness ratio be about 6:1.

In other examples, an alloy consisting essentially oftitanium-nickel-platinum can be provided in a desired ratio as asputtering target. In the alloy approach, a region of conductivematerial comprising titanium and nickel-platinum is provided.

After layer 26B is formed, the structure is exposed to an elevatedtemperature to react layers 26A, 26B, and region of semiconductormaterial 11 to form silicide layers or silicide regions. Layers 26A and26B also react with exposed portions of conductive material 237 and theinnermost one of conductive spacers 217 to form silicides with theseportions as well. More particularly, device 10 preferably is exposed toa temperature in a range from about 650 degrees Celsius through about700 degrees Celsius in the presence of presence of a gas that does notreadily form reaction products with other materials, such as those usedin device 10. By way of example, the anneal step is done in presence ofnitrogen. In one example, a rapid thermal annealing process can be usedwith layers 26A and 26B exposed to one or more predeterminedtemperatures between about 650 degrees Celsius and about 700 degreesCelsius for a time period of about 30 seconds to about 45 seconds. Itwas found through experimentation that temperatures in excess of about700 degrees Celsius can result in stress at the upper corners 141 of themesa regions 140 of device 10 adjacent to dielectric layers 222 ofactive trenches 23, which can result in diminished electricalperformance. In other examples, a furnace anneal can be used.

After the anneal step is completed, the annealed material is exposed toa stripping process remove any unreacted material to Schottky contactregions 26 for device 10. In some examples, the annealed material isexposed to a wet chemical bath comprising sulfuric acid and hydrogenperoxide (SPM). In some examples, the wet chemical bath is heated inexcess of 100 degrees Celsius. In other examples, a wet chemical bathheated to a temperature of about 150 degrees Celsius is used to removeunreacted material to provide Schottky contact regions 26 as illustratedin FIG. 15. As illustrated in FIG. 15 upper surface 222A of dielectricregion 222 is disposed above an upper surface 265 of Schottky contractregions 26.

In subsequent steps, conductive layer 44 is provided overlying majorsurface 18 as illustrated in FIG. 1. In some examples, conductive layer44 can be titanium/titanium-nitride/aluminum-copper or other related orequivalent materials known to those skilled in the art and is configuredas first current carrying electrode or terminal 440 or an anodeelectrode 440 for device 10. Next, substrate 12 can be thinned todecrease its thickness using, for example, a grinding process to providemajor surface 19. Conductive layer 46 can then be provided on majorsurface 19 as described and illustrated in FIG. 1. In some examples,conductive layer 46 can be a solderable metal structure such astitanium-nickel-silver, chromium-nickel-gold, or other related orequivalent materials known by those skilled in the art. In the exampleillustrated, conductive layer 46 provides a second current carryingelectrode or terminal 460 or a cathode electrode 460 for device 10.

One additional advantage of the present description is that a variety ofSchottky barrier heights can be provided using a manufacturing facilitywith only two sputtering chambers, which saves on manufacturing upfrontcosts and ongoing expenses with maintenance and consumables.

FIG. 16 illustrates a partial cross-sectional view of another example ofdevice 10 at a step in fabrication. In the present example, a layer ofmaterial 1026 or layer 1026 is provided overlying major surface 18 ofregion of semiconductor material 11. In accordance with the presentdescription, conductive material 1026 is a combination of metalmaterials configured to provide a predetermined Schottky barrier heightin a desired range. More particularly, the combination of metalcomponents or materials is selected and processed to provide apredetermined Schottky barrier height within a range from about 0.45 eVto about 0.85 eV. Layer 1026 may also be referred to as conductivestructure 1126.

More particularly, in some examples conductive material 1026 comprises anickel-chrome alloy or an as-deposited layer 1026 comprising acombination of materials that include nickel and chrome. In someexamples, layer 1026 comprises an as-deposited layer of nickel-chrome.In other examples, layer 1026 consists essentially of an as-depositedlayer of nickel-chrome. In further examples, conductive material 1026consists of an as-deposited layer of nickel-chrome. In some examples,conductive material 1026 is a nickel-chrome alloy material formed usingsputtering techniques and a sputtering target with a selectednickel-chrome alloy composition. In one example, the sputter target canbe a 40% nickel-60% chrome alloy composition. Other alloy compositionscan be used as well.

In some examples, layer 1026 has an as-formed thickness in a range fromabout 400 Angstroms through about 1300 Angstroms. In other examples,layer 1026 has an as-formed thickness in a range from about 500Angstroms through about 1100 Angstroms. In further examples, layer 1026has an as-formed thickness in a range from about 600 Angstroms throughabout 1000 Angstroms.

In accordance with the present description, after layer 1026 is formed,layer 1026 is exposed to one or more elevated temperatures so that layer1026 forms a silicide layer with region of semiconductor material 11.More particularly, layer 1026 preferably is exposed to one or moretemperatures in a range of 400 degrees Celsius through about 550 degreesCelsius in the presence of presence of a gas that does not readily formreaction products with other materials, such as those used in device 10.By way of example, the annealing step is done in nitrogen. In someexamples, layer 1026 preferably is exposed to one or more temperaturesin a range of 400 degrees Celsius through about 500 degrees. In oneexample, a rapid thermal annealing process can be used with layer 1026exposed to the predetermined temperature(s) between about 400 degreesCelsius and about 500 degrees Celsius for a time period of about 70seconds to about 100 seconds. It was found through experimentation thattemperatures in excess of about 550 to 600 degrees Celsius can result instress at the upper corners 141 of the mesa regions 140 of device 10adjacent to dielectric layers 222 of active trenches 23, which canresult in diminished electrical performance.

After the anneal step is completed, the annealed material is exposed toa stripping or removal process to remove any unreacted material to formor provide Schottky contact regions 26 for device 10. In some examples,the annealed material is exposed to a wet chemical bath comprisingsulfuric acid and hydrogen peroxide (SPM). In some examples, the wetchemical bath is heated to temperatures in excess of 100 degreesCelsius. In other examples, a wet chemical bath heated to a temperatureof about 150 degrees Celsius is used to remove unreacted material toprovide Schottky contact regions 26. In some examples, an etch orremoval time of about 70 minutes through about 90 minutes is used withthe thickness ranges for layer 1026 as described herein.

FIGS. 17 and 18 are box and whisker charts illustrating experimentalresults comparing three variations of device 10 in accordance with thepresent description. FIGS. 17 and 18 are similar to FIGS. 3 and 4 andonly the differences will be described in herein. In particular, acolumn E is added to FIGS. 3 and 4 to provide FIGS. 17 and 18respectively. Column E is data from two wafers of device 10 inaccordance with the present description having a Schottky barrierstructure 26 formed from a layer of nickel-chrome (for example, 40%nickel-60% chrome) having an as-formed thickness of about 1000Angstroms. Columns A, B, C, and D are as described previously inconjunction with FIGS. 3 and 4.

As the data of FIGS. 17 and 18 illustrates, device 10 in accordance withthe present description provides predetermined Schottky barrier heightswithin the range of 0.45 eV to 0.85 eV. In particular, the column Econfiguration of device 10 provides barrier heights from about 0.65 eVto about 0.68 eV with leakage current results that are withinspecification. In addition, the forward voltage at 70 mA is about 0.73 Vfor this configuration, which is within specification.

From all of the foregoing, one skilled in the art can determine thataccording to one example, a method of forming a semiconductor device,includes providing a region of semiconductor material comprising a firstmajor surface and a second major surface opposite to the first majorsurface. The method includes providing a trench structure comprising atrench extending into the region of semiconductor material from thefirst major surface; and a conductive material disposed within thetrench and separated from the region of semiconductor material by adielectric region, wherein the dielectric region is disposed alongopposing sidewall surfaces of the trench and disposed along a lowersurface of the trench; and the dielectric region comprises a firstuppermost surface. The method includes providing a Schottky contactregion disposed adjacent to the first major surface and adjacent to thetrench structure, wherein providing the Schottky contact regioncomprises forming a first layer of material disposed adjacent to thefirst major surface, the first layer of material consisting of titaniumand having a first thickness; forming a second layer of materialdisposed adjacent to the first layer of material, the second layer ofmaterial consisting of nickel-platinum and having a second thickness;exposing the first layer of material and the second layer of material toa temperature in a range from about 650 degrees Celsius through about700 degrees Celsius; and after the step of exposing, removing anyunreacted portions of the first layer of material and the second layerof material.

In a further example, providing the trench structure can compriseproviding the first uppermost surface of the dielectric region extendingabove an upper surface of the Schottky region in a cross-sectional view.In a still further example, providing the Schottky contact regioncomprises providing a first thickness to second thickness ratio greaterthan or equal to 1.33:1. In another example, providing the trenchstructure can comprise providing the first uppermost surface of thedielectric region extending above an upper surface of the Schottkyregion in a cross-sectional view. In a further example, providing theSchottky contact region comprises providing a first thickness to secondthickness ratio of about 6:1. In a still further example, the method canfurther comprise forming a doped region in the region of semiconductoradjacent to the trench structure and adjacent to the Schottky contactregion.

From all of the foregoing, one skilled in the art can determine thataccording to another example, a method of forming a semiconductor devicecan comprise providing a region of semiconductor material comprising afirst major surface and a second major surface opposite to the firstmajor surface. The method includes providing a trench structurecomprising a trench extending into the region of semiconductor materialfrom the first major surface; and a conductive material disposed withinthe trench and separated from the region of semiconductor material by adielectric region. The method includes providing a Schottky contactregion disposed adjacent to the first major surface and adjacent to thetrench structure, wherein providing the Schottky contact regioncomprises forming a layer of material disposed adjacent to the firstmajor surface, the layer of material comprising an as-formed layer ofnickel-chrome and having a first thickness; exposing the layer ofmaterial to a temperature in a range from about 400 degrees Celsiusthrough about 550 degrees Celsius; and after the step of exposing,removing any unreacted portions of the layer of material.

From all of the foregoing, one skilled the art can determine thataccording to a further example, a method of forming a semiconductordevice, can comprise providing a region of semiconductor materialcomprising a first major surface and a second major surface opposite tothe first major surface. The method includes providing a trenchstructure comprising a trench extending into the region of semiconductormaterial from the first major surface; and a conductive materialdisposed within the trench and separated from the region ofsemiconductor material by a dielectric region, wherein the dielectricregion is disposed along opposing sidewall surfaces of the trench anddisposed along a lower surface of the trench; and the dielectric regioncomprises a first uppermost surface. The method includes providing aSchottky contact region disposed adjacent to the first major surface andadjacent to the trench structure, wherein providing the Schottky contactregion comprises forming a first layer of material disposed adjacent tothe first major surface, the first layer of material consistingessentially of nickel-chrome and having a first thickness; exposing thefirst layer of material to a temperature in a range from about 400degrees Celsius through about 550 degrees Celsius; and after the step ofexposing, removing any unreacted portions of the first layer ofmaterial.

From all of the foregoing, one skilled in the art can determine thataccording to a still further example, a method of forming asemiconductor device can comprise providing a region of semiconductormaterial comprising a first major surface and a second major surfaceopposite to the first major surface. The method includes providing atrench structure comprising a trench extending into the region ofsemiconductor material from the first major surface; and a conductivematerial disposed within the trench and separated from the region ofsemiconductor material by a dielectric region, wherein: the dielectricregion is disposed along opposing sidewall surfaces of the trench anddisposed along a lower surface of the trench; and the dielectric regioncomprises a first uppermost surface. The method includes providing aSchottky contact region disposed adjacent to the first major surface andadjacent to the trench structure, wherein providing the Schottky contactregion comprises forming a first layer of material disposed adjacent tothe first major surface, the first layer of material consisting of anas-formed layer of nickel-chrome having a thickness; exposing the firstlayer of material to a temperature in a range from about 400 degreesCelsius through about 550 degrees Celsius; and after the step ofexposing, removing any unreacted portions of the first layer ofmaterial.

In view of all of the above, it is evident that a novel structure andmethod of making the structure are disclosed. Included, among otherfeatures, is a Schottky contact region formed from a combination ofconductive materials including titanium and nickel-platinum or acombination of conductive materials including a nickel-chrome alloy. Insome examples, a layer of titanium if provided first following by alayer of nickel-platinum. In other examples, a layer of nickel-chrome isprovided. The combination of conductive materials is then exposed to apredetermined elevated temperature to form a silicide region within thesemiconductor device. The combination of materials provides Schottkybarrier heights within a desired 0.45 eV to 0.85 eV range, provides asemiconductor device with improved power dissipation, and provides asemiconductor device with reduced stress-related defects, which, amongother things, reduces leakage current. In addition, the combination ofconductive layers reduces the amount of silicide migration in the areaof the trench gate oxide, which further improves device performance. Thestructure and method can be implemented into existing process flows,which saves on manufacturing costs and cycle time.

While the subject matter of the invention is described with specificpreferred embodiments and example embodiments, the foregoing drawingsand descriptions thereof depict only typical examples of the subjectmatter, and are not therefore to be considered limiting of its scope. Itis evident that many alternatives and variations will be apparent tothose skilled in the art.

As the claims hereinafter reflect, inventive aspects may lie in lessthan all features of a single foregoing disclosed example. Thus, thehereinafter expressed claims are hereby expressly incorporated into thisDetailed Description of the Drawings, with each claim standing on itsown as a separate example of the invention. Furthermore, while someexamples described herein include some but not other features includedin other examples, combinations of features of different examples aremeant to be within the scope of the invention and meant to formdifferent examples as would be understood by those skilled in the art.

What is claimed is:
 1. A method of forming a semiconductor device,comprising: providing a region of semiconductor material comprising afirst major surface and a second major surface opposite to the firstmajor surface; providing a trench structure comprising: a trenchextending into the region of semiconductor material from the first majorsurface; and a conductive material disposed within the trench andseparated from the region of semiconductor material by a dielectricregion; providing a Schottky contact region disposed adjacent to thefirst major surface and adjacent to the trench structure, whereinproviding the Schottky contact region comprises: forming a layer ofmaterial disposed adjacent to the first major surface, the layer ofmaterial comprising an as-formed layer of nickel-chrome and having afirst thickness; exposing the layer of material to a temperature in arange from about 400 degrees Celsius through about 550 degrees Celsius;and after the step of exposing, removing any unreacted portions of thelayer of material.
 2. The method of claim 1, wherein: forming the layerof material comprises forming the layer of material consistingessentially of nickel-chrome.
 3. The method of claim 1, wherein: formingthe layer of material comprises forming the layer of material consistingof nickel-chrome.
 4. The method of claim 1, wherein: forming the layerof material comprises forming the layer of material comprising a 40%nickel-60% chrome alloy material.
 5. The method of claim 1, wherein:forming the layer of material comprises providing the first thickness ina range from about 400 Angstroms through about 1300 Angstroms.
 6. Themethod of claim 1, wherein: forming the layer of material comprisesproviding the first thickness in a range from about 500 Angstromsthrough about 1100 Angstroms.
 7. The method of claim 1, wherein: formingthe layer of material comprises providing the first thickness in a rangefrom about 600 Angstroms through about 1000 Angstroms.
 8. The method ofclaim 1, further comprising: forming a conductive layer overlying theSchottky contact region.
 9. The method of claim 1, wherein: providingthe trench structure comprises providing an active trench structure. 10.The method of claim 1, wherein: exposing the layer of material to thetemperature comprises exposing to a temperature in a range from about400 degrees Celsius to about 500 degrees Celsius.
 11. The method ofclaim 10, wherein: exposing the layer of material to the temperaturecomprises exposing for a time. period from about 70 seconds to about 100seconds.
 12. A method of forming a semiconductor device, comprising:providing a region of semiconductor material comprising a first majorsurface and a second major surface opposite to the first major surface;providing a trench structure comprising: a trench extending into theregion of semiconductor material from the first major surface; and aconductive material disposed within the trench and separated from theregion of semiconductor material by a dielectric region, wherein thedielectric region is disposed along opposing sidewall surfaces of thetrench and disposed along a lower surface of the trench; and thedielectric region comprises a first uppermost surface. providing aSchottky contact region disposed adjacent to the first major surface andadjacent to the trench structure, wherein providing the Schottky contactregion comprises: forming a first layer of material disposed adjacent tothe first major surface, the first layer of material consistingessentially of nickel-chrome and having a first thickness; exposing thefirst layer of material to a temperature in a range from about 400degrees Celsius through about 550 degrees Celsius; and after the step ofexposing, removing any unreacted portions of the first layer of material13. The method of claim 12, wherein: forming the layer of materialcomprises forming the layer of material comprising a 40% nickel-60%chrome alloy material.
 14. The method of claim 12, wherein: forming thelayer of material comprises providing the first thickness in a rangefrom about 400 Angstroms through about 1300 Angstroms.
 15. The method ofclaim 12, wherein: providing the trench structure comprises providingthe first uppermost surface of the dielectric region extending above anupper surface of the Schottky region in a cross-sectional view.
 16. Themethod of claim 12, further comprising: forming a conductive layeroverlying the Schottky contact region, wherein: providing the trenchstructure comprises providing an active trench structure; and exposingthe layer of material comprises exposing for a time period of about 70seconds to about 100 seconds.
 17. The method of claim 12, wherein:providing the region of semiconductor material comprises: providing asemiconductor substrate; and providing a semiconductor layer overlyingthe substrate; the semiconductor layer includes the first major surface;and the semiconductor layer comprises a non-uniform dopant profile overits thickness.
 18. A method of forming a semiconductor device,comprising: providing a region of semiconductor material comprising afirst major surface and a second major surface opposite to the firstmajor surface; providing a trench structure comprising: a trenchextending into the region of semiconductor material from the first majorsurface; and a conductive material disposed within the trench andseparated from the region of semiconductor material by a dielectricregion, wherein: the dielectric region is disposed along opposingsidewall surfaces of the trench and disposed along a lower surface ofthe trench; and the dielectric region comprises a first uppermostsurface; and providing a Schottky contact region disposed adjacent tothe first major surface and adjacent to the trench structure, whereinproviding the Schottky contact region comprises: forming a conductivestructure, the conductive structure being one of: a layer of materialconsisting essentially of nickel-chrome disposed adjacent to the firstmajor surface; or a first layer of material consisting essentially oftitanium disposed adjacent to the first major surface and a second layerof material disposed adjacent to the first layer of material andconsisting essentially of nickel-platinum; exposing the conductivestructure to an elevated temperature to form a silicide structure; andafter the step of exposing, removing any unreacted portions of theconductive structure.
 19. The method of claim 18, wherein: forming theconductive structure comprises: forming the first layer of materialconsisting essentially of titanium and having a first thickness; andforming the second layer of material consisting essentially ofnickel-platinum and having a second thickness; exposing comprisesexposing the first layer of material and the second layer of material toa temperature in a range from about 650 degrees Celsius through about700 degrees Celsius; and forming the conductive structure comprisesproviding a first thickness to second thickness ratio greater than orequal to 1.33:1.
 20. The method of claim 18, wherein: forming theconductive structure comprises: forming the layer of material consistingessentially of nickel-chrome and having a thickness in a range fromabout 500 Angstroms through about 1100 Angstroms; exposing comprisesexposing the layer of material to a temperature in a range from about400 degrees Celsius through about 550 degrees Celsius.